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Espressif Systems /ESP32-S3 /WCL /Core_0_MESSAGE_PHASE

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Interpret as Core_0_MESSAGE_PHASE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_0_MESSAGE_MATCH)CORE_0_MESSAGE_MATCH 0CORE_0_MESSAGE_EXPECT 0 (CORE_0_MESSAGE_DATAPHASE)CORE_0_MESSAGE_DATAPHASE 0 (CORE_0_MESSAGE_ADDRESSPHASE)CORE_0_MESSAGE_ADDRESSPHASE

Description

Clear writer_buffer status register

Fields

CORE_0_MESSAGE_MATCH

This bit indicates whether the check is successful
CORE_0_MESSAGE_EXPECT

This field indicates the data to be written next time
CORE_0_MESSAGE_DATAPHASE

If this bit is 1, it means that is checking clear write_buffer operation,and is checking data
CORE_0_MESSAGE_ADDRESSPHASE

If this bit is 1, it means that is checking clear write_buffer operation,and is checking address.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data